As is well known, the manufacturing cost of an integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the elements of the active components such as gate electrodes, by semiconductor technology, and by diffused regions such as transistor source and drain regions and bipolar emitter and base regions. Isolation structures surrounding various active devices also contribute to area on the integrated circuit, but improve device performance, for example, by electrically isolating adjacent transistors.
One known structure for electrically isolating active devices from each other is known as localized oxidation of silicon, or LOCOS, as described in U.S. Pat. No. 5,260,229, issued Nov. 9, 1993 to Hodges et al. and U.S. Pat. No. 5,543,343, issued Aug. 6, 1996 to Bryant et al. which are incorporated by reference. But unfortunately, this approach tends to require fairly large separations (ca. eight microns (.mu.m)) between active devices on the integrated circuit.
Another parameter, that often must be scaled down in size to produce a highly reliable yet compact semiconductor device is the thickness of the dielectrics employed, for example, as gate dielectrics of MOS transistors. Scaling dielectric layers to produce thinner dielectric layers that are also highly reliable as gate dielectrics has proven to be difficult. For example, gate dielectrics are typically made of pure silicon dioxide (SiO.sub.2), which is thermally grown or deposited. The integrity of silicon dioxide decreases as the thickness of the layer decreases, producing more defects, for example, pinholes. The inability to produce uniform, reliable, and thin, SiO.sub.2 gate insulators causes device failures and makes thinnings of these layers impractical.